Circuit and method for refreshing data stored in a memory cell

ABSTRACT

An IC includes a memory array that has memory cells for storing data and that refreshes the data stored in a memory cell during a respective refresh cycle of a refresh mode. The integrated circuit also includes a refresh circuit that during a first portion of the refresh mode implements a first series of refresh cycles in the memory array at a first frequency and that during a second portion of the refresh mode implements a second series of refresh cycles in the memory array at a second frequency. Such a refresh circuit allows longer internal row-line on times during a self-refresh mode without affecting the auto-refresh TRC, which is the specified maximum time that the IC requires to execute an auto-refresh cycle. Therefore, the IC can consume less power during a self-refresh mode and still meet the same auto-refresh specification.

TECHNICAL FIELD

[0001] The invention relates generally to integrated circuits (ICs), andmore particularly to an IC that includes an improved circuit andimplements an improved method for refreshing data stored in a memorycell. Such a circuit and method allow a significant decrease in therefresh frequency, and thus a significant decrease in power consumption,while the IC is in a self-refresh mode.

BACKGROUND OF THE INVENTION

[0002] System designers continually push IC manufactures to design ICs,such as volatile-memory ICs, that have lower power requirements,particularly during low-power, i.e., “sleep”, modes. Unfortunately, asdiscussed below, it is difficult for IC manufacturers to reduce thesleep-mode power consumed by ICs that include volatile memory cells.

[0003] Because the data stored in a volatile memory cell—such as adynamic-random-access-memory (DRAM) cell—degrades relatively quickly,the data must be periodically refreshed. Therefore, an IC that includesone or more volatile memory cells periodically implements refreshcycles.

[0004] During a typical refresh cycle, a sense amplifier reads the datastored in the memory cell and then writes the same data back into thecell. More specifically, the cell stores a signal level, such as avoltage level, that represents the value of the stored data. Forexample, a voltage level of Vdd often represents a data value of logic1, and a voltage level of ground (0 V) often represents a data value oflogic 0. Unfortunately, well-known phenomena such as memory-cell leakagecause this signal level to decay over time. If this signal level is notmaintained, then it may decay to a point where it represents a datavalue different than the data value originally stored in the memorycell. For example, a voltage level of Vdd (logic 1) may decay toward 0 V(logic 0), and if not maintained, may eventually become close enough to0 V to represent logic 0 instead of logic 1. To maintain the storedsignal level, the IC containing the memory cell implements a refreshcycle during which the sense amplifier receives the signal level fromthe cell, amplifies the signal level to its full value (i.e., Vdd forlogic 1 and 0 V for logic 0), and provides the full signal level to thecell for storage.

[0005] During normal operation of an IC that contains a volatile memorycell, the electronic system incorporating the IC periodically issues anauto-refresh command to refresh the cell. For example, the IC mayinclude multiple rows of memory cells and a refresh address counter thatindicates the row to be refreshed. Each auto-refresh command causes theIC to implement a respective auto-refresh cycle during which the ICrefreshes the cells in the addressed row and increments or decrementsthe counter by one. After all of the rows have been refreshed, thecounter “turns over” so that the IC can continue to refresh the rows.

[0006] To insure that the system issues auto-refresh commands frequentlyenough to prevent the memory cells from losing their respective data,the IC manufacturer specifies the maximum refresh period that can elapsebetween successive refreshes of a memory cell. For example, suppose thatthe IC must refresh each memory cell at least once every 64 milliseconds(ms), includes 4,096 (4 k) rows of memory cells, and refreshes an entirerow during each refresh cycle. Then, to insure that no memory cells losetheir respective data, the system must execute at least 4,096auto-refresh commands (one for each row) every 64 ms. The system canissue these auto-refresh commands all at once (burst auto refresh), orcan distribute them over the 64 ms refresh period (distributed autorefresh).

[0007] Furthermore, to insure that the refresh cycles are long enough toallow the IC to adequately refresh a memory cell, the IC manufacturespecifies the minimum duration that the system must allow for eachrefresh cycle. Therefore, once the system issues an auto-refreshcommand, it must wait at least this minimum duration before issuinganother command to the IC. For example, if the IC takes 70 nanoseconds(ns) to implement a refresh cycle, then the system must wait at least 70ns after issuing an auto-refresh command before issuing another commandto the IC.

[0008] To increase the speed rating—and thus the price—of the IC, themanufacturer often specifies the shortest possible duration for eachrefresh cycle. Often, this duration is too short to allow the IC torefresh a memory cell to its full signal level. As discussed below, thismay require the IC manufacturer to specify a shorter refresh periodbetween successive refreshes of a memory cell. Also as discussed below,a shorter refresh period requires the memory to issue internal refreshcommands more frequently during the self-refresh mode, and thus maycause the IC to draw more power during a self-refresh mode.

[0009]FIG. 1 is a plot of the broken-line charge/discharge curves 10 and12 for a memory cell that the IC only partially refreshes. That is, theIC implements a refresh cycle that is too short to allow the memory cellto acquire a full signal level. In this example, Vdd/2 is the thresholdlevel between logic 1 and logic 0. Referring to the curve 10, at timet1, a memory cell storing a logic 1—which here corresponds to Vdd—iscoupled to the respective digit line to begin the refresh cycle. Becausethe digit line is capacitive, the cell voltage drops and the digit-linevoltage—which is represented by the solid curve 11—rises to a startingvoltage Vs1. Furthermore, because the digit-line capacitance isapproximately five times greater than the cell capacitance, the cellvoltage drops more than the digit-line voltage rises. Starting at timet2, the IC charges the memory cell over a refresh time Trefresh.Typically, Trefresh is a portion of the total refresh-cycle time. Forexample, if the refresh-cycle time is 70 ns, Trefresh may be 60 ns. Asshown, Trefresh isn't long enough for the IC to fully charge the memorycell to Vdd. Consequently, the IC can only partially charge the memorycell to V1, which is lower than Vdd. For example, V1 may be 100-300millivolts (mV) lower than Vdd. After Trefresh elapses, the memory celldischarges to Vdd/2 over a discharge time Tdischarge, which isproportional to V1. Thus, the higher V1, the longer Tdischarge, and thelower V1, the shorter Tdischarge. The shorter Tdischarge, the morefrequently the IC must refresh the signal level stored in the memorycell, and thus the shorter the maximum refresh period that the ICmanufacturer can specify. A similar analysis applies to the curves 12and 13, which corresponds to the memory cell storing logic 0.

[0010] During low-power operation of the system such as during a “sleep”mode, the system issues a self-refresh command that causes the IC toenter a self-refresh mode. During a self-refresh mode—which is typicallya low-power mode of the IC—the IC typically ignores all system commands(other than a “wake-up” command) and performs few if any functions otherthan automatically refreshing the memory cells. Because it ignoresauto-refresh commands during the self-refresh mode, the IC includesself-refresh circuitry that automatically implements self-refresh cyclesduring the self-refresh mode. Except for the automatic implementation,the self-refresh cycles are similar to auto-refresh cycles.

[0011]FIG. 2 is a plot of the peak and average currents that the ICdraws during a self-refresh mode. The peak current Ipeak is the totalrefresh current that the IC draws during a respective self-refresh cycleto recharge the memory cell or cells being refreshed. Each self-refreshcycle has the refresh time Trefresh during which the IC draws therefresh current. And in this example, the self-refresh cycles are evenlydistributed throughout the self-refresh period, one every Trefperseconds. For example, Trefresh=60 ns and Trefper=20 microseconds (μs).The average current lavg is proportional to Ipeak, Trefresh, and theIC's power consumption, and is inversely proportional to Trefper.

[0012] To save power in the self-refresh mode, the IC designers oftenreduce the average current lavg by designing the IC to implement thelongest possible self-refresh period between successive self-refreshesof a memory cell. Typically, the designers can lengthen the self-refreshperiod beyond the specified auto-refresh period, and thus can lengthenTrefper beyond the maximum time specified between evenly distributedauto-refresh cycles. For example, using the above values, if thespecified maximum auto-refresh period is 64 ms, then an evenlydistributed auto refresh requires one auto-refresh cycle every (64ms/4096 rows)=15.6 μs. The designers, however, may design the IC suchthat the self-refresh period is approximately 82 ms, which correspondsto Trefper ˜20 μs during a self-refresh mode.

[0013] Unfortunately, because during normal operation the shortauto-refresh cycles prevent the IC from fully refreshing the storeddata, the IC designers cannot further lengthen Trefper without riskingdata corruption during the self-refresh mode.

SUMMARY OF THE INVENTION

[0014] In one aspect of the invention, an IC includes a memory arrayhaving memory cells for storing data. The memory array refreshes thedata stored in each memory cell during a respective refresh cycle of arefresh mode. The IC also includes a refresh circuit that is coupled tothe memory array, that during a first portion of the refresh modeimplements a first series of refresh cycles in the memory array at afirst frequency, and that during a second portion of the refresh modeimplements a second series of refresh cycles in the memory array at asecond frequency.

[0015] In another aspect of the invention, an IC includes a memory arrayand refresh circuit. During a first refresh mode, the refresh circuitimplements in the memory array a refresh cycle having a refresh portionof a first duration, and during a second refresh mode the refreshcircuit implements a refresh cycle having a refresh portion of a secondduration.

[0016] Thus, such an IC can achieve a high-speed rating by implementingrelatively fast auto-refresh cycles during normal operation and canachieve power savings during a self-refresh mode by implementing longerTrefper times between self-refresh cycles.

BRIEF DESCRIPTION OF THE DRAWINGS

[0017]FIG. 1 is a graph of the charge/discharge curves for a memory cellthat is only partially refreshed during a conventional refresh cycle.

[0018]FIG. 2 is a graph of the peak and average currents drawn by aconventional IC during a self-refresh mode.

[0019]FIG. 3 is a block diagram of a refresh circuit and a memory arrayaccording to an embodiment of the invention.

[0020]FIG. 4 is a graph of the charge/discharge curves for a memory cellthat is refreshed by the refresh circuit of FIG. 3 during a self-refreshmode.

[0021]FIG. 5 is a graph of the peak burst, peak maintenance, and averagecurrents drawn during a self-refresh mode by an IC that includes therefresh circuit of FIG. 3.

[0022]FIG. 6 is a timing diagram for an embodiment of the refreshcircuit of FIG. 3.

[0023]FIG. 7 is a schematic diagram of an embodiment of the resetcircuit of FIG. 3.

[0024]FIG. 8 is a schematic diagram of an embodiment of thefrequency-control circuit of FIG. 3.

[0025]FIG. 9 is a schematic block diagram of an embodiment of therefresh clock generator of FIG. 3.

[0026]FIG. 10 is a timing diagram for an embodiment of the refresh clockgenerator of FIG. 9.

[0027]FIG. 11 is a schematic block diagram of an embodiment of thesense-amplifier control circuit of FIG. 3.

[0028]FIG. 12 is a block diagram of an embodiment of a memory circuitthat includes the refresh circuit and memory array of FIG. 3.

[0029]FIG. 13 is a block diagram of an embodiment of an electronicsystem that includes the memory circuit of FIG. 12.

DETAILED DESCRIPTION OF THE INVENTION

[0030]FIG. 3 is a block diagram of refresh circuit 20 for implementing aself-refresh mode in a memory array 22. Typically, the circuit 20 andthe array 22 are part of an IC that receives a SELF-REFRESH signal fromthe system in which it is installed. The circuit 20 implements aself-refresh mode that has an initial burst portion to fully refresh allof the memory cells in the array 22 and that has a subsequentmaintenance portion to refresh the cells at the maximum possibleself-refresh period. Thus, as discussed below, the circuit 20 allows asignificant increase in Trefper (FIG. 2), and thus provides asignificant power savings, during the maintenance portion of theself-refresh mode.

[0031] The circuit 20 includes a reset circuit 24 for generating aREFRESH signal in response to SELF-REFRESH.

[0032] A refresh clock-frequency control circuit 26 generates aFREQUENCY CONTROL signal that has a first state during the initial burstportion of the self-refresh mode and that has a second state during thesubsequent maintenance portion of the self-refresh mode. A refresh clockgenerator 28 generates a CLOCK signal that has a relatively high burstfrequency during the burst portion of the self-refresh mode and arelatively low maintenance frequency during the maintenance portion. TheCLOCK signal, however, is not the same as the external clock signalreceived by the IC that incorporates the refresh circuit 20. Therefore,“CLOCK” refers to the signal generated by the generator 28 unless statedotherwise.

[0033] A refresh address generator 30 addresses the memory cell, row ofmemory cells, or column of memory cells to be refreshed during arespective self-refresh cycle. In one embodiment, the generator 30 is acounter that resets to an initial address at the beginning of theself-refresh mode and then increments/decrements the address once duringeach period of CLOCK.

[0034] A sense-amplifier control circuit 32 controls the length of theTrefresh (FIG. 1 and FIG. 4) time during self-refresh to allow fullrefresh of the memory cells in the array 22. In some embodiments, thecontrol circuit 32 may also control the length of the Trefresh timeduring auto-refresh, and may control the sense-amplifier on time duringread and write cycles. Specifically, during a self-refresh mode, thecontrol circuit 32 activates the respective ones of the sense amplifiers34 in the memory array 22 for a predetermined Trefresh time during eachself-refresh cycle Trefper. Trefper is synonymous with the self-refreshcycle in this disclosure. In one embodiment, the control circuit 32activates the respective sense amplifiers 34 for a Trefresh time ofapproximately 80 ns during each Trefper such that these sense amplifiershave sufficient time to fully refresh the respective memory cells. In anembodiment where the control circuit 32 also controls the length of theTrefresh time during an auto-refresh cycle, the control circuit 32activates the sense amplifiers 34 for a Trefresh time that issignificantly shorter than the Trefresh time during the self-refreshmode. For example, the auto-refresh Trefresh time may be 60 ns, whichmay be insufficient to allow the sense amplifiers 34 to fully refreshthe respective memory cells. This shorter auto-refresh Trefresh time,however, allows the IC to achieve a higher speed rating by decreasingthe auto-refresh cycle time. That is to say, the auto-refresh iscompleted sooner and the IC is ready for a new instruction.

[0035]FIG. 4 is a graph of charge/discharge curves 34 and 36 for amemory cell of the array 22 (FIG. 3) that is fully refreshed during aself-refresh cycle implemented by the refresh circuit 20 (FIG. 3). Fullyrefreshing the memory cell significantly increases Tdischarge, and thusallows the refresh circuit 20 to significantly increase the distributedself-refresh refresh Trefper during the maintenance portion of theself-refresh mode.

[0036]FIG. 5 is a graph of the peak current Ipeak during the burst andmaintenance portions of the self-refresh mode implemented by the circuit20 (FIG. 3) and the average current lavg during the maintenance portion.During the initial burst portion, the circuit 20 implements oneself-refresh cycle after another to fully refresh all the memory cellsfast enough to prevent corruption of the stored data. For example, ifthe Trefresh time of each cycle is 80 ns as discussed above, then eachrefresh cycle Trefper is approximately 90-100 ns. For 4096 rows, theburst portion is thus approximately 400 μs long, which is fast enough toprevent data loss. During the subsequent maintenance portion of theself-refresh mode, because the cells are now fully refreshed, thedistributed self-refresh cycle time Trefper is maximized to lower lavgand thus the power consumed by the IC. For example, in one embodiment,Trefper for the circuit 20 is approximately 30 μs as compared toapproximately 20 μs for prior-art ICs. This corresponds to a 20% to 30%decrease in the IC's power consumption during the maintenance portion ofthe self-refresh mode. Although the IC's power consumption is higherduring the burst portion of the self-refresh mode, one typically startsto realize a power savings after the circuit 20 has been in theself-refresh mode long enough to refresh all of the memory cells onetime. This power savings increases the longer the IC remains in theself-refresh mode.

[0037] The operation of the circuit 20 of FIG. 3 is now discussed inconjunction with the timing diagram of FIG. 6. Because thesense-amplifier control circuit 32 typically ignores the PRECHARGE andACTIVATE signals during a self-refresh mode, these signals are notincluded in the timing diagram.

[0038] The system initiates a self-refresh mode in the IC bytransitioning SELF REFRESH from logic 0 to logic 1. In response to thistransition, the reset circuit 24 transitions RESET from logic 0 to logic1 for a predetermined time. In response to this transition of RESET, theaddress generator 30 resets to an initial address such as 0. In responseto the transition of RESET and the logic 1 for FREQUENCY CONTROL, theclock generator 28 generates CLOCK at the burst frequency F1, which isapproximately 0.4-0.8 MHz ({fraction (1/F1)}=T1=1.25 us to 2.5 us) inone embodiment. In response to the rising edges of CLOCK and the logic 1for SELF REFRESH, the control circuit 32 generates ROW-LINE ON pulsesthat fire the respective addressed rows in the array 22. The controlcircuit 32 also generates SENSE-AMP CONTROL pulses having widths ofTrefresh, which in one embodiment is approximately 80 ns as stated aboveto allow the sense amplifiers 34 to fully refresh the memory cells inthe array 22. The rising edges of the ROW-LINE ON pulses are typically5-15 ns before the rising edges of the respective SENSE-AMP CONTROLpulses to allow time for the addressed row to fire before the senseamplifiers 34 are activated. The control circuit 32 also generatesROW-LINE OFF pulses that turn off the addressed rows to end therespective self-refresh cycles. Therefore, the ROW-LINE ON pulse firesROW 0 of the array 22, and the SENSE-AMP CONTROL pulse causes the senseamplifiers 34 to refresh the memory cells in ROW 0. In response tosubsequent rising edges of CLOCK, the address generator 30 incrementsthe row address by one so that the circuit 20 refreshes subsequent rowsof memory cells in a similar manner.

[0039] When the address generator generates the highest row address X,the frequency control circuit 26 transitions FREQUENCY CONTROL fromlogic 1 to logic 0. In response to this transition, the clock generator28 generates CLOCK at a maintenance frequency F2, which is significantlylower than the burst frequency F1, to enter the maintenance portion ofthe self-refresh mode. The maintenance portion is similar to the burstportion except for the lower CLOCK frequency F2, and lasts until thesystem “wakes up” the IC by transitioning SELF REFRESH back to logic 0.In one embodiment, F2=F1/16 is approximately 25-50 KHz (Trefper=20-40μs), for example 33.3 KHz (Trefper=30 μs). Thus, the maintenancefrequency F2 allows the IC to draw less average current during themaintenance portion of the self-refresh mode, and thus allows the IC toconsume less power than prior-art ICs during the self-refresh mode.Furthermore, the sense amplifiers 34 refresh the last row, ROW X, inresponse to the first rising edge of CLOCK in the maintenance portion.That is, ROW X is not refreshed during the burst portion. But thiscauses no data loss because ROW X is still refreshed well before thedata stored in its cells becomes corrupted.

[0040] Still referring to FIGS. 3 and 6, although specific embodimentsof the refresh circuit 20 are discussed, other embodiments are possible.For example, the active and inactive logic levels of the signals in FIG.6 may be changed. Furthermore, the address generator 30 may decrementthe address instead of incrementing it. Additionally, the circuit 20 mayrefresh some but not all of the rows during the burst portion of theself-refresh mode. The actual number of rows refreshed during the burstportion is unimportant as long as enough rows are refreshed so that allof the cells in the array 22 can be fully refreshed within the specifiedrefresh period. Moreover, instead of implementing an initial burstportion with a relatively high CLOCK frequency and a subsequentmaintenance portion with a lower CLOCK frequency, the circuit 20 maygradually decrease the CLOCK frequency until it reaches the minimumfrequency F2. This gradual technique, however, may take longer than thedescribed burst-maintenance technique to realize a power savings.

[0041]FIG. 7 is a schematic diagram of an embodiment of the refreshcircuit 24 of FIG. 3. The refresh circuit is a “one-shot” that includesan inverter 40, which receives SELF REFRESH and which is seriallyconnected to a delay circuit 42. A NAND gate 44 has one input coupled tothe output of the circuit 42 and another input that receives SELFREFRESH. The output of the NAND gate 44 is coupled to the input of aninverter 46, which generates RESET. Before the system initiates theself-refresh mode, RESET equals logic 0 and SELF REFRESH has equaledlogic 0 for a significant length of time. If the system transitions SELFREFRESH to logic 1, then the output of the inverter 40 transitions tologic 0. But the delay element 42 maintains its output at logic 1 for adelay period, which equals approximately 1-2 ns in one embodiment. Thus,the inputs to the NAND gate 44 are temporarily both at logic 1, the NANDgate generates a logic 0, and the inverter 46 generates logic 1 forRESET. After the delay period of the element 42 has elapsed, the logic 0at the output of the inverter 40 propagates to the output of the delay42, the NAND gate 44 generates logic 1, and the inverter 46 generateslogic 0 for RESET.

[0042]FIG. 8 is a schematic diagram of an embodiment of the frequencycontrol circuit 26 of FIG. 3. Generally, before the system initiates aself-refresh mode and thus when both RESET and SELF REFRESH equal logic0, FREQUENCY CONTROL equals logic 1 regardless of the values of theaddress bits A₀-A_(n) from the address generator 30. Thus, when thesystem transitions SELF REFRESH to logic 1 to initiate the self-refreshmode, the refresh circuit 20 starts with the burst portion. During theself-refresh mode when the address attains it last value before “turningover”, then the circuit 26 transitions FREQUENCY CONTROL to logic 0,thus ending the burst portion and beginning the maintenance portion ofthe self-refresh mode. In this embodiment, this last address is all ofthe address bits A₀-A_(n) equaling logic 1, although the circuit 26 canbe designed to recognize any address as the last address.

[0043] More specifically, before the self-refresh mode when SELF REFRESHand RESET equal logic 0, an inverter 48 and NAND gate 50 each generateslogic 1 and an inverter 52 generates logic 0. This logic 0 causes a NANDgate 54 to generate logic 1 regardless of the address-dependent logicvalue generated by a NOR gate 56. Furthermore, because SELF REFRESH islogic 0, a NAND gate 58 generates logic 1 for FREQUENCY CONTROLregardless of the logic value generated by a NAND gate 60, which iscoupled to the NAND gate 58 in a sequential configuration.

[0044] After SELF REFRESH transitions to logic 1 and RESET transitionsto logic 1 and back to logic 0, but before the address generator 30reaches the last address, the inverter 48 generates logic 1, the NANDgate 50 generates logic 0, and the inverter 52 generates logic 1.Because the address generator 30 has not reached the last address, atleast one of the address bits A₀-A_(n) equals logic 0. Thus, at leastone of the NAND gates 62 ₀-62 _(y), which each receive a respective pairof the address bits A₀-A_(n), outputs logic 1, and the NOR gate 56outputs logic 0. This logic 0 causes the NAND gate 54 to continue togenerate a logic 1. Because FREQUENCY CONTROL also equals logic 1, theNAND gate 60 generates logic 0, which causes the NAND gate 58 tomaintain FREQUENCY CONTROL at logic 1.

[0045] When the address generator reaches the last address, and thus allof the address bits A₀-A_(n) equal logic 1, all of the NAND gates 62₀-62 _(y) generate logic 0, and the NOR gate 56 generates logic 1.Because the inverter 52 also generates logic 1, the NAND gate 54generates logic 0, which causes the NAND gate 60 to generate logic 1.Because both SELF REFESH and the output of the NAND gate 60 equal logic1, the NAND gate 58 transitions FREQUENCY CONTROL to logic 0, thusending the burst portion of the self-refresh mode.

[0046] When SELF REFRESH transitions to logic 0 to end the self-refreshmode, the NAND gate 58 resets FREQUENCY CONTROL to logic 1 inpreparation for the next implementation of the self-refresh mode.

[0047]FIG. 9 is a schematic block diagram of the clock generator 28 ofFIG. 3. The generator 28 includes a self-refresh oscillator 64 forreceiving SELF REFRESH and for generating a burst clock signal CLOCK1having the burst frequency F1 if SELF REFRESH equals logic 1. In oneembodiment, the oscillator 64 is a conventional ring oscillator. Thegenerator 28 also includes a maintenance oscillator 66 for generating amaintenance clock signal CLOCK2 having the maintenance frequency F2. Inone embodiment, the oscillator 66 is a conventional counter. Forexample, if the oscillator 66 is a 4-bit counter, then it generatesF2=F1/16. A multiplexer 68 receives FREQUENCY CONTROL, couples CLOCK1 tothe clock output terminal 69 as CLOCK if FREQUENCY CONTROL equals logic1, and couples CLOCK2 to the clock output terminal 69 as CLOCK ifFREQUENCY CONTROL equals logic 0. In one embodiment, the multiplexer 68includes an inverter 70 and conventional switch circuits 72 and 74.

[0048] The operation of the clock generator 28 is now discussed withreference to FIG. 9 and the timing diagram of FIG. 10.

[0049] Before the system initiates a self-refresh mode, SELF REFRESHequals logic 0, which deactivates the burst oscillator 64. Furthermore,FREQUENCY CONTROL equals logic 1, which activates the switch circuit 74to couple CLOCK1 to the terminal 69 as CLOCK. But because the burstoscillator 64 is inactive, then both CLOCK1 and CLOCK are at a constantlogic value, here logic 0.

[0050] At the beginning of the self-refresh mode, SELF REFRESHtransitions to logic 1, which activates the burst oscillator 64 togenerates CLOCK1. FREQUENCY CONTROL is logic 1, which deactivates theswitch circuit 72 and activates the switch circuit 74 to couple CLOCK1to the terminal 69 as CLOCK.

[0051] At the end of the burst portion of the self-refresh mode,FREQUENCY CONTROL transitions to logic 0 to enter the maintenanceportion of the self-refresh mode. This deactivates the switch circuit 74and activates the switch circuit 72 to couple CLOCK2 to the terminal 69as CLOCK.

[0052] At a subsequent time, SELF REFRESH transitions to logic 0 to endthe self-refresh mode, and FREQUENCY CONTROL transitions to logic 1 inpreparation of the next self-refresh mode.

[0053]FIG. 11 is a block diagram of an embodiment of the sense-amplifiercontrol circuit 32 of FIG. 3. In this embodiment, the circuit 32generates SENSE-AMP CONTROL during both auto-refresh and self-refreshcycles as well as during non-refresh cycles such as normal read andwrite cycles.

[0054] The circuit 32 includes a RAS circuit 80, which duringnon-refresh operation generates the SENSE-AMP CONTROL, ROW-LINE ON, andNON-REFRESH ROW-LINE OFF signals in response to the ACTIVATE andPRECHARGE signals in a conventional manner.

[0055] During a refresh mode, the control circuit 32 uses a feedbackloop that includes the RAS circuit 80, an auto-refresh delay circuit 82,a self-refresh delay circuit 84, and a multiplexer 86. The rising-edge(logic 0 to logic 1) and falling-edge (logic 1 to logic 0) feedbackdelays of the loop respectively set the pulse width Trefresh ofSENSE-AMP CONTROL and the pulse width of ROW-LINE OFF as discussedbelow.

[0056] In addition to the ACTIVATE and PRECHARGE signals, the circuit 80receives SELF-REFRESH, CLOCK, and REFRESH ROW-LINE OFF, which is thefeedback signal. During a refresh mode, the circuit 80 generates theROW-LINE ON and SENSE-AMP CONTROL pulses in response to SELF-REFRESH andCLOCK.

[0057] The auto-refresh delay circuit 82, which is a single-edge delaycircuit, delays the rising edge of SENSE-AMP CONTROL for a period thatequals the refresh time of an auto-fresh cycle, and imparts little or nodelay to the falling edge of SENSE-AMP CONTROL.

[0058] The self-refresh delay circuit 84, which is also a single-edgedelay circuit, further delays the rising edge of SENSE-AMP CONTROL foran additional period during a self-refresh cycle, and imparts little orno additional delay to the falling edge of SENSE-AMP CONTROL. The sumsof the rising-edge delays introduced by the auto-refresh andself-refresh delay circuits 82 and 84 equals the refresh time during aself-refresh cycle. Thus, as discussed above, the self-refresh delaycircuit 84 extends the Trefresh time during a self-refresh cycle toallow full refresh of the memory cells in the array 22 (FIG. 3).

[0059] The multiplexer 86 includes conventional switch circuits 88 and90, which receive SELF REFRESH, bypass the self-refresh delay circuit 84during an auto-refresh cycle, couple the circuit 84 into the feedbackloop during a self-refresh mode, and generate REFRESH ROW-LINE OFF on anoutput terminal 91.

[0060] A multiplexer 92 includes conventional switch circuits 94 and 96,which receive a REFRESH signal, couple NON-REFRESH ROW-LINE OFF to thearray 22 as the ROW-LINE OFF signal during a non-refresh mode, andcouple REFRESH ROW-LINE OFF to the array 22 as the ROW-LINE OFF signalduring both a self-refresh and an auto-refresh mode.

[0061] Referring to FIGS. 6 and 11, the operation of the sense-amplifiercontrol circuit 32 is discussed.

[0062] During an auto-refresh cycle, the rising edge of CLOCK triggersthe RAS circuit 80 to generate the rising edge of ROW-LINE ON, whichfires the row to be refreshed. After a time sufficient to allow thefiring signal to propagate to the end of the fired row line, the circuit80 generates the rising edge of SENSE-AMP CONTROL, which turns on theappropriate ones of the sense amps 34 (FIG. 3). Because SELF REFRESHequals logic 0, the switch circuit 88 is inactive and the switch circuit90 is active. The active switch circuit 90 directly couples the outputof the auto-refresh delay circuit 82 to the multiplexer output terminal91. After the auto-refresh delay time, the rising edge of SENSE-AMPCONTROL propagates to the output of the auto-refresh delay circuit 82.In response to this rising edge, the switch circuit 90 generates therising edge of REFRESH ROW-LINE OFF, which turns off the fired row whilethe sense amps 34 are on. This rising edge also resets the circuit 80,which, after an inherent internal delay time, generates the falling edgeof SENSE-AMP CONTROL, which turns off the sense amps 34. Because theauto-refresh delay circuit 82 provides little or no falling-edge delay,the switch circuit 90 generates the falling edge of REFRESH ROW-LINE OFFsoon after the falling edge of SENSE-AMP CONTROL. The circuit 80 is nowreset until it receives another rising edge of CLOCK.

[0063] In one embodiment, the rising- and falling-edge delays of the RAScircuit 80 are approximately 15 ns, the rising- and falling-edge delaysof the auto-refresh delay circuit 82 are approximately 45 ns and 3-5 ns,respectively, and the rising- and falling-edge delays of the switchcircuit 90 are less than 1 ns. Therefore, in this embodiment, the totalrising-edge delay, i.e., refresh time Trefresh (FIG. 6), during anauto-refresh cycle is approximately 60 ns.

[0064] During a self-refresh cycle, the operation of the sense-amplifiercontrol circuit 32 is similar except that SENSE-AMP CONTROL propagatesthrough both the auto-refresh and self-refresh delay circuits 82 and 84.Specifically, the rising edge of CLOCK triggers the RAS circuit 80 togenerate the rising edge of ROW-LINE ON, which fires the row to berefreshed. After a time sufficient to allow the firing signal topropagate to the end of the fired row line, the circuit 80 generates therising edge of SENSE-AMP CONTROL, which turns on the appropriate ones ofthe sense amps 34 (FIG. 3). Because SELF REFRESH equals logic 1, theswitch circuit 90 is inactive and the switch circuit 88 is active. Theactive switch circuit 88 directly couples the output of the self-refreshdelay circuit 84 to the multiplexer output terminal 91. After a delaytime that equals the sum of the auto-refresh and self-refresh delaytimes, the rising edge of SENSE-AMP CONTROL propagates through theauto-refresh and self-refresh delay circuits 82 and 84 to the input ofthe switch circuit 88. In response to this rising edge at its input, theswitch circuit 88 generates the rising edge of REFRESH ROW-LINE OFF,which turns off the fired row while the sense amps 34 are on. Thisrising edge also resets the circuit 80, which, after an inherentinternal delay time, generates the falling edge of SENSE-AMP CONTROL,which turns off the sense amps 34. Because the auto-refresh andself-refresh delay circuits 82 and 84 provide little or no falling-edgedelays, the switch circuit 88 generates the falling edge of REFRESHROW-LINE OFF soon after the falling edge of SENSE-AMP CONTROL. Thecircuit 80 is now reset until it receives another rising edge of CLOCK.

[0065] In one embodiment, the rising- and falling-edge delays of theself-refresh delay circuit 84 are approximately 20 ns and 3-5 ns,respectively, and the rising- and falling-edge delays of the switchcircuit 88 are less than 1 ns. Therefore, in this embodiment, the totalrising-edge delay, i.e., refresh time Trefresh (FIG. 6), during aself-refresh cycle is approximately 80 ns, which is approximately 20 nslonger than during an auto-refresh cycle. This extra 20 ns is sufficientto allow the sense amplifiers 34 (FIG. 3) to fully refresh the memorycells in the array 22! That is, this extra 20 ns allows sufficient timeto charge a cell to the maximum voltage Vdd or to discharge the cell tothe minimum voltage 0.

[0066]FIG. 12 is a block diagram of an embodiment of a memory circuit100, which includes the refresh circuit 20 of FIG. 3.

[0067] The memory circuit 100 includes an address register 102, whichreceives an address from an ADDRESS bus. A control logic circuit 104receives an external clock (CLK) signal, and receives clock enable(CKE), chip select, chip select (CS), row address strobe (RAS), columnaddress strobe (CAS), write enable (WE), and the SELF REFRESH signalsfrom the COMMAND bus, and communicates with the other circuits of thememory device 100. In the illustrated embodiment, the control circuit104 includes the refresh circuit 20, although the refresh circuit 20 maybe located elsewhere in other embodiments.

[0068] A row address multiplexer 106 receives the address signal fromthe address register 102 and provides the row address to the row-addresslatch-and-decode circuits 108 a and 108 b for the memory bank 110 a or110 b, respectively. During read and write cycles, the row-addresslatch-and-decode circuits 108 a and 108 b activate the word lines of theaddressed rows of memory cells in the memory banks 120 a and 120 b,respectively. Read/write circuits 112 a and 112 b read data from theaddressed memory cells in the memory banks 110 a and 110 b,respectively, during a read cycle, and write data to the addressedmemory cells during a write cycle. A column-address latch-and-decodecircuit 114 receives the address from the address register 102 andprovides the column address of the selected memory cells to theread/write circuits 112 a and 112 b. For clarity, the address register102, the row-address multiplexer 106, the row-address latch-and-decodecircuits 108 a and 108 b, and the column-address latch-and-decodecircuit 114 can be collectively referred to as an address decoder.

[0069] A data input/output (I/O) circuit 116 includes a plurality ofinput buffers 118. During a write cycle, the buffers 108 receive andstore data from the DATA bus, and the read/write circuits 112 a and 112b provide the stored data to the memory banks 110 a and 100 b,respectively. The data I/O circuit 116 also includes a plurality ofoutput drivers 120. During a read cycle, the read/write circuits 112 aand 112 b provide data from the memory banks 110 a and 110 b,respectively, to the drivers 120, which in turn provide this data to theDATA bus.

[0070] The memory device 100 may also include an optional charge pump126, which steps up the power-supply voltage V_(DD) to a voltageV_(DDP). In one embodiment, the pump 126 generates V_(DDP) approximately1-1.5 V higher than V_(DD). The memory circuit 100 may also use V_(DDP)to conventionally overdrive selected internal transistors.

[0071]FIG. 13 is a block diagram of an electronic system 130, such as acomputer system, that incorporates the memory circuit 100 of FIG. 12.The system 130 includes computer circuitry 132 for performing computerfunctions, such as executing software to perform desired calculationsand tasks. The circuitry 132 typically includes a processor 134 and thememory circuit 100, which is coupled to the processor 134. One or moreinput devices 136, such as a keyboard or a mouse, are coupled to thecomputer circuitry 132 and allow an operator (not shown) to manuallyinput data thereto. One or more output devices 138 are coupled to thecomputer circuitry 132 to provide to the operator data generated by thecomputer circuitry 132. Examples of such output devices 138 include aprinter and a video display unit. One or more data-storage devices 140are coupled to the computer circuitry 132 to store data on or retrievedata from external storage media (not shown). Examples of the storagedevices 140 and the corresponding storage media include drives thataccept hard and floppy disks, tape cassettes, and compact disk read-onlymemories (CD-ROMs). Typically, the computer circuitry 132 includesaddress data and command buses and a clock line that are respectivelycoupled to the ADDRESS, DATA, and COMMAND buses, and the CLK line of thememory circuit 100.

[0072] From the foregoing it will be appreciated that, although specificembodiments of the invention have been described herein for purposes ofillustration, various modifications may be made without deviating fromthe spirit and scope of the invention.

What is claimed:
 1. An integrated circuit, comprising: a memory arrayhaving memory cells for storing data, the memory array operable torefresh the data stored in a memory cell during a respective refreshcycle of a refresh mode; and a refresh circuit coupled to the memoryarray, the refresh circuit operable during a first portion of therefresh mode to implement a first series of refresh cycles in the memoryarray at a first frequency, the refresh circuit operable during a secondportion of the refresh mode to implement a second series of refreshcycles in the memory array at a second frequency.
 2. The integratedcircuit of claim 1 wherein: the data stored in the memory cells hasrespective signal levels; and the memory array includes a senseamplifier that is operable to refresh the data stored in a memory cellduring a respective refresh cycle by amplifying the signal level of thedata and coupling the amplified signal level to the memory cell.
 3. Theintegrated circuit of claim 1 wherein: the data stored in each of thememory cells has a respective signal level within a first range if thedata equals a first logic value and has a respective signal level in asecond range if the data equals a second logic value, the first range ofsignal levels having a maximum signal level, the second range of signallevels having a minimum signal level; the memory array includes a senseamplifier that is operable to refresh the data stored in each memorycell during a respective refresh cycle by amplifying the signal level ofthe data and coupling the amplified signal level to the memory cell; andthe refresh circuit is operable to activate the sense amplifier for arefresh portion of each refresh cycle, the refresh portion having aduration sufficient to allow the sense amplifier to refresh the datastored in a memory cell to substantially the maximum signal level if thedata equals the first logic value and to refresh the data stored in thememory cell to substantially the minimum signal level if the data equalsthe second logic value.
 4. The integrated circuit of claim 1 wherein:the data stored in each of the memory cells has a respective signallevel within a first range if the data equals logic 1 and has arespective signal level in a second range if the data equals logic 0,the first range of signal levels having a maximum signal level, thesecond range of signal levels having a minimum signal level; the memoryarray includes a sense amplifier that is operable to refresh the datastored in each memory cell during a respective refresh cycle byamplifying the signal level of the data and coupling the amplifiedsignal level to the memory cell; and the refresh circuit is operable toactivate the sense amplifier for a refresh portion of each refreshcycle, the refresh portion having a duration sufficient to allow thesense amplifier to refresh the data stored in a memory cell tosubstantially the maximum signal level if the data equals logic 1 and torefresh the data stored in the memory cell to substantially the minimumsignal level if the data equals logic
 0. 5. The integrated circuit ofclaim 1 wherein: the data stored in each of the memory cells has arespective signal level within a first range if the data equals logic 0and has a respective signal level in a second range if the data equalslogic 1, the first range of signal levels having a maximum signal level,the second range of signal levels having a minimum signal level; thememory array includes a sense amplifier that is operable to refresh thedata stored in each memory cell during a respective refresh cycle byamplifying the signal level of the data and coupling the amplifiedsignal level to the memory cell; and the refresh circuit is operable toactivate the sense amplifier for a refresh portion of each refreshcycle, the refresh portion having a duration sufficient to allow thesense amplifier to refresh the data stored in a memory cell tosubstantially the maximum signal level if the data equals logic 0 and torefresh the data stored in the memory cell to substantially the minimumsignal level if the data equals logic
 1. 6. The integrated circuit ofclaim 1 wherein: the memory array refreshes the respective data in eachof the memory cells once during the first portion of the refresh mode;and the first frequency is significantly higher than the secondfrequency.
 7. The integrated circuit of claim 1 wherein the refresh modecomprises a self-refresh mode.
 8. An integrated circuit, comprising: amemory array having memory cells for storing data, the memory arrayoperable to refresh the data stored in a memory cell during a respectiverefresh cycle; and a refresh circuit coupled to the memory array, therefresh circuit operable during a first refresh mode to implement in thememory array a refresh cycle having a refresh portion of a firstduration, the refresh circuit operable during a second refresh mode toimplement in the memory array a refresh cycle having a refresh portionof a second duration.
 9. The integrated circuit of claim 8 wherein: thesecond duration is significantly longer than the first duration; thefirst refresh mode comprises an auto-refresh mode; and the secondrefresh mode comprises a self-refresh mode.
 10. The integrated circuitof claim 8 wherein: the first duration approximately equals 60nanoseconds; and the second duration approximately equals 80nanoseconds.
 11. The integrated circuit of claim 8 wherein: the datastored in each of the memory cells has a respective signal level withina first range if the data equals a first logic value and has arespective signal level in a second range if the data equals a secondlogic value, the first range of signal levels having a maximum signallevel, the second range of signal levels having a minimum signal level;the memory array includes a sense amplifier that is operable to refreshthe data stored in each memory cell during a respective refresh cycle byamplifying the signal level of the data and coupling the amplifiedsignal level to the memory cell; and the refresh circuit is operable toactivate the sense amplifier for the first duration during the refreshportion of the first refresh cycle and for the second duration duringthe refresh portion of the second refresh cycle, the first durationbeing insufficient and the second duration being sufficient to allow thesense amplifier to refresh the data stored in a respective memory cellto substantially the maximum signal level if the data equals the firstlogic value and to refresh the data stored in the memory cell tosubstantially the minimum signal level if the data equals the secondlogic value.
 12. An integrated circuit, comprising: a memory arrayhaving memory cells for storing data, the memory cells arranged in oneor more rows that each include a respective one or more memory cells,the memory array operable to refresh the data stored in the memory cellor cells of a row during a respective refresh cycle of a refresh mode;and a refresh circuit coupled to the memory array, the refresh circuitoperable during a first portion of the refresh mode to implement a firstseries of refresh cycles in the memory array at a first frequency, therefresh circuit operable during a second portion of the refresh mode toimplement a second series of refresh cycles in the memory array at asecond frequency that is significantly lower than the first frequency.13. An integrated circuit, comprising: a memory array having memorycells for storing data, the memory cells arranged in one or more rowsthat each include a respective one or more memory cells, the memoryarray operable to refresh the data stored in the memory cell or cells ofa row during a respective refresh cycle of a refresh mode; and a refreshcircuit coupled to the memory array, the refresh circuit operable duringa first refresh mode to implement in the memory array a refresh cyclehaving a refresh portion of a first duration, the refresh circuitoperable during a second refresh mode to implement in the memory array arefresh cycle having a refresh portion of a second duration that issignificantly longer than the first duration.
 14. An integrated circuit,comprising: a memory array having memory cells for storing data, thememory array operable to receive a refresh address and to refresh thedata stored in a memory cell located at the refresh address during arespective refresh cycle of a refresh mode; a refresh clock circuitoperable to generate a refresh clock signal having a first frequencyduring a first portion of the refresh mode and having a second frequencyduring a second portion of the refresh mode, each period of the clocksignal corresponding to a respective refresh cycle, the first frequencybeing significantly higher than the second frequency; and a refreshaddress circuit coupled to the memory array and to the refresh clockcircuit, the refresh address circuit operable to generate the refreshaddress and to update the refresh address once during each period of therefresh clock signal.
 15. The integrated circuit of claim 14 wherein therefresh address circuit is operable to update the refresh address byincrementing the refresh address by
 1. 16. The integrated circuit ofclaim 14 wherein: the data stored in each of the memory cells has arespective signal level within a first range if the data equals a firstlogic value and has a respective signal level in a second range if thedata equals a second logic value, the first and second ranges of signallevels having respective first and second full signal levels; the memoryarray includes a sense amplifier that is operable to refresh the datastored in a memory cell during a respective refresh cycle by amplifyingthe signal level of the data and coupling the amplified signal level tothe memory cell; and a sense-amplifier control circuit coupled to thememory array and to the refresh clock circuit, the sense-amplifiercircuit operable to activate the sense amplifier during a respectiverefresh portion of each refresh cycle, the refresh portion having aduration that causes the sense amplifier to refresh the data stored in arespective memory cell to substantially the first full signal level ifthe data equals the first logic value and to substantially the secondfull signal level if the data equals the second logic value.
 17. Theintegrated circuit of claim 14 , further comprising: the refresh clockcircuit operable to receive a clock-frequency control signal and togenerate the refresh clock signal having the first frequency if theclock-frequency control signal has a first state and to generate therefresh clock signal having the second frequency if the clock-frequencycontrol signal has a second state; and a clock-frequency control circuitcoupled to the refresh address and clock circuits, the clock-frequencycontrol circuit operable to generate the clock-frequency control signalhaving the first state from the beginning of the refresh mode until therefresh address circuit has generated respective addresses for apredetermined number of memory cells, the clock-frequency controlcircuit operable to generate the clock-frequency control signal havingthe second state for a remainder of the refresh mode.
 18. An integratedcircuit, comprising: a memory array including memory cells for storingdata having respective signal levels, the memory array operable toreceive a refresh address, the memory array also including a senseamplifier that is operable to refresh the data stored in a memory celllocated at the refresh address during a respective refresh cycle byamplifying the signal level of the data and coupling the amplifiedsignal level to the memory cell; a refresh address circuit coupled tothe memory array and operable to receive a refresh clock signal, therefresh address circuit operable to generate the refresh address and toupdate the refresh address during each cycle of the refresh clocksignal; and a sense-amplifier control circuit coupled to the memoryarray and operable to activate the sense amplifier for a respectivefirst period of each refresh cycle during a first refresh mode and for arespective second period of each refresh cycle during a second refreshmode, the first period being long enough to allow the sense amplifier toonly partially refresh the data stored in a respective memory cell, thesecond period being long enough to allow the sense amplifier tosubstantially fully refresh the data stored in the respective memorycell.
 19. The integrated circuit of claim 18 , wherein thesense-amplifier control circuit comprises: a circuit having an inputterminal, a feedback terminal, and an output terminal, the circuitoperable to generate a sense-amplifier activation signal on the outputterminal; a first delay circuit; and a feed-back loop coupled betweenthe output and feedback terminals of the circuit and including a seconddelay circuit and a delay-select circuit serially coupled to the seconddelay circuit and coupled to the first delay circuit, the delay-selectcircuit operable to serially couple the first delay circuit to thesecond delay circuit during the first refresh mode and to bypass thefirst delay circuit during the second refresh mode.
 20. An integratedcircuit, comprising: a memory array including memory cells for storingdata and having refresh address and refresh duration input terminals; arefresh address generator having a refresh clock input terminal andhaving refresh address output terminals respectively coupled the refreshaddress input terminals of the memory array; a refresh clock circuithaving a clock output terminal coupled to the clock input terminal ofthe refresh address generator, the refresh clock circuit operable togenerate a refresh clock signal on the clock output terminal, therefresh clock signal having a first frequency during a first portion ofa refresh mode and having a second frequency during a second portion ofthe refresh mode; and a refresh duration circuit having a clock inputterminal coupled to the clock output terminal of the refresh clockcircuit and having an output terminal coupled to the refresh durationinput terminal of the memory array.
 21. The integrated circuit of claim20 wherein the refresh address generator has a reset input terminal. 22.The integrated circuit of claim 20 wherein the refresh duration circuithas a refresh-mode terminal.
 23. The integrated circuit of claim 20wherein the memory array includes a sense amplifier coupled to thememory cells.
 24. The integrated circuit of claim 20 , furthercomprising: the refresh clock generator having a clock-frequency inputterminal; and a clock-frequency control circuit having an outputterminal coupled to the clock-frequency input terminal of the refreshclock generator and having a refresh-mode terminal.
 25. The integratedcircuit of claim 20 , further comprising: the refresh clock generatorhaving a clock-frequency input terminal; and a clock-frequency controlcircuit having an output terminal coupled to the clock-frequency inputterminal of the refresh clock generator, a refresh-mode terminal, andaddress input terminals respectively coupled to the address outputterminals of the refresh address generator.
 26. The integrated circuitof claim 20 , further comprising: the refresh clock generator having aclock-frequency input terminal; and a clock-frequency control circuithaving an output terminal coupled to the clock-frequency input terminalof the refresh clock generator, a refresh-mode terminal, a resetterminal, and address input terminals respectively coupled to theaddress output terminals of the refresh address generator.
 27. Anintegrated circuit, comprising: a memory array including memory cellsfor storing data and having address and refresh duration inputterminals; a refresh address generator having a refresh clock inputterminal and having address output terminals coupled the addressterminals of the memory array; a refresh clock circuit having a clockoutput terminal coupled to the refresh clock input terminal of therefresh address generator; and a refresh duration circuit having arefresh clock input terminal coupled to the clock output terminal of therefresh clock circuit and having an output terminal coupled to therefresh duration input terminal of the memory array, the refreshduration circuit operable to cause the memory array to implement a firstrefresh duration per refresh cycle during a first refresh mode and toimplement a second refresh duration per refresh cycle during a secondrefresh mode.
 28. The integrated circuit of claim 27 wherein one of thefirst and second refresh durations is sufficient to substantially fullyrefresh the data stored in a memory cell.
 29. An electronic system,comprising: a data input device; a data output device; and a computercircuit coupled to the data input and output devices and including aprocessor and a memory circuit coupled to the processor, the memorycircuit including: a memory array having memory cells for storing data,the memory array operable to refresh the data stored in a memory cellduring a respective refresh cycle of a refresh mode; and a refreshcircuit coupled to the memory array, the refresh circuit operable duringa first portion of the refresh mode to implement a first series ofrefresh cycles in the memory array at a first frequency, the refreshcircuit operable during a second portion of the refresh mode toimplement a second series of refresh cycles in the memory array at asecond frequency that is significantly slower than the first frequency.30. An electronic system, comprising: a data input device; a data outputdevice; and a computer circuit coupled to the data input and outputdevices and including a processor and a memory circuit coupled to theprocessor, the memory circuit including: a memory array having memorycells for storing data, the memory array operable to refresh the datastored in a memory cell during a respective refresh cycle; and a refreshcircuit coupled to the memory array, the refresh circuit operable duringa first refresh mode to implement in the memory array a refresh cyclehaving a refresh portion of a first duration, the refresh circuitoperable during a second refresh mode to implement in the memory array arefresh cycle having a refresh portion of a second duration that issignificantly longer than the first duration.
 31. A method, comprising:implementing a first group of data refresh cycles at a first frequencyduring a first portion of a refresh mode; and implementing a secondgroup of data refresh cycles at a second frequency during a secondportion of the refresh mode.
 32. The method of claim 31 wherein therefresh mode comprises a self-refresh mode.
 33. The method of claim 31wherein: the first portion comprises an initial portion of the refreshmode; and the first frequency is significantly higher than the secondfrequency.
 34. The method of claim 31 , further comprising refreshingstored data to substantially full signal levels during the refreshcycles of one of the first and second groups.
 35. The method of claim 31wherein the implementing the first group of refresh cycles comprisesimplementing a sufficient number of refresh cycles in the first groupsuch that the second frequency can be long enough for the second groupof refresh cycles to substantially fully refresh data stored in an arrayof memory cells without causing corruption of the data.
 36. A method,comprising: refreshing data stored in a memory cell for a first durationduring a refresh cycle of a first refresh mode; and refreshing datastored in the memory cell for a second duration during a refresh cycleof a second refresh mode.
 37. The method of claim 36 wherein: the secondduration is significantly longer than the first duration; the firstrefresh mode comprises an auto-refresh mode; and the second refresh modecomprises a self-refresh mode.
 38. The method of claim 36 wherein: therefreshing the stored data for the first duration comprises partiallyrefreshing the stored data; and the refreshing the stored data for thesecond duration comprises substantially fully refreshing the storeddata.